1. Field of the Invention
The present invention relates to a plastic sealed type semiconductor apparatus, and more particularly, to a plastic sealed type semiconductor apparatus which is highly reliable and hence suited for high integration.
2. Description of the Prior Art
Conventional plastic sealed semiconductor apparatus has the structure in which a semiconductor device is fixed on a chip pad which is the device mounting portion with a plurality of leads disposed around the chip pad, in which the semiconductor device and the leads are electrically connected by thin metal wires and in which a resin is molded around the entire assembly.
In recent years, there has been an increasing demand for semiconductor apparatuses in which a plurality of semiconductor devices are mounted on the chip pad to achieve a high degree of integration. Japanese Patent Unexamined Publication Nos. 62-119952, 1-257361 and 60-47161 disclose a structure in which a plurality of semiconductor devices are fixed onto chip pads in the conventional manner.
While the structure in which a plurality of semiconductor devices are mounted has been studied to achieve a high degree of integration, the size of a single semiconductor device has been increased also to achieve a high degree of integration. However, there is a tendency that the external dimensions, particularly, the external dimensions in the direction of the plane, of the semiconductor apparatus cannot be increased or is reduced due to design restrictions of the substrate on which the semiconductor apparatus is mounted.
Under the circumstances, in the structures in which the semiconductor devices are fixed on the chip pads in the conventional manner, when the size of each of the semiconductor devices is increased but the external dimensions of the semiconductor apparatus remains the same, the length of that portion of the semiconductor apparatus which fixes the leads to the resin (the length of the inner lead which is buried in the resin) is reduced. Thus, there is raised a problem that fixing strength is not sufficiently provided to the lead.
To avoid this problem, Japanese Patent Unexamined Publication No. 61-241959 has proposed a structure in which a plurality of inner leads are adhered to the circuit forming surface of a semiconductor device with an insulating member therebetween. This structure is called a lead-on-chip configuration.
FIG. 17 illustrates an example of a plastic sealed type semiconductor apparatus in which two semiconductor devices having the lead-on-chip structure are laid on top of one another, which apparatus is the subject of this invention.
As shown in FIG. 17, electric signal leads 2 and 2' are adhered to circuit forming surfaces 1a and 1'a of semiconductor devices 1 and 1' with an insulating member 3 provided therebetween for electric insulation between the semiconductor devices 1 and 1' and the leads 2 and 2'. Electric connection between the semiconductor devices 1 and 1' and the electric signal leads 2 and 2' is provided by means of thin metal wires 4.
The two semiconductor devices having the lead-on-chip structure are disposed in such a manner that the circuit forming surfaces thereof oppose each other. The electric signal leads 2 and 2' are joined to each other at an overlaid portion 2a thereof. A resin 5 is molded around the semiconductor devices and the electric signal leads to form a resin package 6. Whereas the electric signal lead 2' is cut substantially at the same level as the side surface of the resin package 6, only the electric signal lead 2 is coupled to an outer lead 7.
Thus, plastic sealed semiconductor apparatus is provided by overlaying the lead-on-chip type semiconductor devices on top of each other, so that the outer dimensions of the semiconductor apparatus do not increase even when the semiconductor devices employed are large, and sufficient fixing strength of the leads is provided.
However, in the plastic sealed semiconductor apparatus in which the lead-on-chip type semiconductor devices are overlaid on top of each other, as shown in FIG. 17, since the joined portions of the electric signal leads 2 and 2' are restricted in only a little area, there is space on a major portion of the overlaid surfaces of the electric signal leads 2 and 2' so that water or moisture readily enter the interior of the plastic package 6 through the overlaid surfaces of the electric signal leads 2 and 2'.
When the water or moisture enters the interior of the plastic package 6, this can corrode or break the electric interconnections or thin metal wires 4 formed on the circuit forming surfaces 1a and 1'a of the semiconductor devices 1 and 1', substantially reducing the reliability of the plastic sealed type semiconductor apparatus. Thus, entry of water or moisture into the interior of the plastic molded type semiconductor apparatus must be prevented.